Part 7 — CPU Architecture and Assembly

Caches, Cache Lines, TLB, MMU, MPU

This chapter covers the memory hierarchy that sits between the CPU and main memory: caches, cache lines, the TLB, and the MMU/MPU.

Why This Matters

Memory access dominates many programs' performance. Cache behavior — locality, cache lines, and false sharing — often matters more than instruction count. The MMU/MPU are what make virtual memory and memory protection real.

Prerequisites

c.cpu.1 — CPU execution.

Core Concept

Caches

Caches are small, fast memories between the CPU and RAM. The hierarchy is usually L1 (smallest, fastest), L2, L3 (larger, slower). On a miss, a whole cache line (typically 64 bytes) is fetched from the next level.

Cache lines

Memory is transferred in fixed-size blocks called cache lines. Accessing any byte in a line pulls in the whole line, so spatial locality (using nearby bytes) is fast.

TLB

The TLB caches virtual-to-physical page translations, accelerating the MMU. A TLB miss walks page tables and is expensive.

MMU

The MMU translates virtual addresses to physical addresses and enforces permissions (read/write/execute). It is what gives each process an isolated address space.

MPU

An MPU (common on microcontrollers) enforces memory regions and permissions but does not translate addresses (no virtual memory).

Examples

Cache-friendly vs. unfriendly

/* good: contiguous, one element per cache line visit */
for (int i = 0; i < N; i++) sum += a[i];

/* bad: stride 16, touches one element per line, wastes bandwidth */
for (int i = 0; i < N; i += 16) sum += a[i];

How It Works

On each load/store, the CPU checks L1, then L2, then L3, then RAM. A hit returns data in a few cycles; a miss costs tens to hundreds of cycles. The TLB is checked in parallel with the cache (VIPT) or before it (PIPT).

Variations

Cache associativity

Caches are direct-mapped, set-associative, or fully associative, trading hit rate for complexity. This affects conflict misses.

Cache coherence

In multicore systems, a coherence protocol (e.g., MESI) keeps caches consistent, which is why false sharing (c.perf.5) hurts.

Common Mistakes

Ignoring cache-line effects (false sharing, strided access).
Assuming virtual addresses equal physical addresses.
Accessing memory that is not cache-coherent (DMA) without maintenance.

Undefined Behavior

C-level UB (e.g., writing to rodata) can cause an MMU permission fault, but

the MMU behavior is hardware/OS, not ISO C.

Portability

Cache sizes, line sizes, and TLB behavior are hardware-specific.

Under the Hood

The MMU walks multi-level page tables, caching translations in the TLB. Caches use tags (address bits) to find lines. The MPU checks region attributes without translation.

Practical Usage

Write cache-friendly code: contiguous access, avoid large strides.
Keep hot data together and align to cache lines to avoid false sharing.
In embedded code, understand MPU region configuration.

Exercises

1. Benchmark stride-1 vs. stride-16 access to see cache effects. 2. Query cache line size (POSIX sysconf(_SC_LEVEL1_DCACHE_LINESIZE)). 3. Explain why the TLB matters for large working sets.

Deep Challenge

Explain how false sharing arises from cache lines, and write a program that demonstrates the slowdown on a multicore machine, then fix it with padding or alignment.

c.perf.2 — cache locality.
c.perf.5 — false sharing.
c.mem.virtual — virtual memory.

References

CPU architecture manuals (Intel, ARM), OS memory docs.

Verification

Cache/TLB/MMU/MPU behavior is hardware-specific. HARDWARE
No example was executed during generation unless noted. `Execution not

verified.`

Progress

[ ] Read
[ ] Understand
[ ] Complete examples
[ ] Complete exercises
[ ] Complete deep challenge

Concept checkboxes

[ ] Cache hierarchy
[ ] Cache lines
[ ] TLB
[ ] MMU
[ ] MPU

Mastery levels

Concept	Current level (0–8)	Target level
c.cpu.cache	0	6
c.cpu.cache-line	0	6
c.cpu.tlb	0	5
c.cpu.mmu	0	6
c.cpu.mpu	0	5

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