Architectures: x86, x86-64, ARM, ARM64, RISC-V

This chapter surveys the major CPU architectures you will encounter in C systems work: x86/x86-64, ARM/ARM64, and RISC-V.

Why This Matters

C is portable across architectures, but systems and embedded work often targets a specific one. Knowing the families — their register models, calling conventions, and instruction-set character — helps you read assembly and understand performance.

Prerequisites

• c.cpu.1 — CPU fundamentals.

Core Concept

Key Characteristics

x86 / x86-64

• Variable-length instructions, many registers (x86-64 adds 8 general regs

+ 16 in total).

• Rich addressing modes.
• Backward-compatible with x86.

ARM / ARM64

• Fixed-width 32-bit (ARM) or 32-bit (ARM64) instructions.
• Load/store architecture, many registers, predication (ARM).
• Thumb (16-bit) mode for code density on ARM.
• ARM64 has 31 general-purpose registers plus SP/zero register.

RISC-V

• Open, modular ISA; base integer set + extensions.
• 32 registers; load/store; clean design.

Examples

Same C, different assembly

int add(int a, int b) { return a + b; }

x86-64:

add:
    lea eax, [rdi + rsi]
    ret

ARM64:

add:
    add w0, w0, w1
    ret

RISC-V (RV64):

add:
    addw a0, a0, a1
    ret

How It Works

Each architecture defines registers, instructions, and an ABI. The compiler's back end emits target-specific code; the same C source compiles to different assembly per target.

Variations

32-bit vs. 64-bit

The same family has 32-bit and 64-bit variants with different register widths and ABIs (e.g., ARM vs. AArch64).

Extensions

SIMD extensions differ: SSE/AVX on x86, NEON/SVE on ARM, vector extensions on RISC-V.

Common Mistakes

• Assuming one architecture's calling convention on another.
• Hard-coding assembly or intrinsics for a single architecture.

Undefined Behavior

• Architecture-specific code (inline asm, intrinsics) is not ISO C and is

constrained by the target.

Portability

• Write portable C; isolate architecture-specific code behind feature

detection (c.pp.conditional).

Under the Hood

The compiler targets an architecture via its back end. Cross compilers produce code for a target different from the host (c.build.9).

Practical Usage

• Know your target architecture for embedded/firmware work.
• Use -march/-mcpu to target specific features.
• Read the right architecture manual when writing inline asm/intrinsics.

Exercises

1. Compile the same function for x86-64 and ARM64 (cross compiler if available) and compare. 2. Look up the register sets of ARM64 and RISC-V. 3. Explain the difference between ARM and ARM64 (AArch64).

Deep Challenge

Explain how a calling convention differs between x86-64 System V and ARM64 AAPCS, and write a small C function, then compare its generated prologue/ epilogue on both.

Related Concepts

• c.cpu.1 — CPU fundamentals.
• c.cpu.6 — C-to-assembly.
• c.build.9 — cross compilation.

References

• Intel SDM, ARM ARM, RISC-V spec.

Verification

• Architecture characteristics are hardware facts. HARDWARE
• No example was executed during generation unless noted. `Execution not

verified.`

Progress

• [ ] Read
• [ ] Understand
• [ ] Complete examples
• [ ] Complete exercises
• [ ] Complete deep challenge

Concept checkboxes

• [ ] x86 and x86-64
• [ ] ARM and ARM64
• [ ] RISC-V
• [ ] Architecture differences

Mastery levels